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Utils: Add support for some more useful arm extensions#18422

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Whatcookie:armFeatures
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Utils: Add support for some more useful arm extensions#18422
Whatcookie wants to merge 3 commits intoRPCS3:masterfrom
Whatcookie:armFeatures

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@Whatcookie
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Adds support for some more modern ARMV8 features that might be useful for RPCS3:

FEAT_LUT is like pshufb/tbl but with compressed indices. Might be useful for emulating FSM

FEAT_I8MM adds another dot product instruction, and 8 bit matrix multiplication instructions. Might be useful for GBH/GBB.

Add a function for detecting SVE length. We might need to guard use of SVE in SPU emulation behind a check that the SVE length is exactly 128b.

@Wunkolo
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Wunkolo commented Mar 22, 2026

fwiw, detection of ARM CPU features on windows follows a pattern of checking specially named entries in the registry over in HKEY_LOCAL_MACHINE\HARDWARE\DESCRIPTION\System\CentralProcessor.
For example(From my thinkpad x13s):

CP 4000: MIDR_EL1
CP 4020: ID_AA64PFR0_EL1
CP 4021: ID_AA64PFR1_EL1
CP 4028: ID_AA64DFR0_EL1
CP 4029: ID_AA64DFR1_EL1
CP 402C: ID_AA64AFR0_EL1
CP 402D: ID_AA64AFR1_EL1
CP 4030: ID_AA64ISAR0_EL1
CP 4031: ID_AA64ISAR1_EL1
CP 4038: ID_AA64MMFR0_EL1
CP 4039: ID_AA64MMFR1_EL1
CP 403A: ID_AA64MMFR2_EL1

The CP #### format is based on the encoding of the register's identifier when passed into the MRS instruction: (op0&1):op1:crn:crm:op2.
Reading the ID_AA64ISAR2_EL1 register on Windows to detect FEAT_LUT in this case would be in a CP 4032 registry-entry.

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fwiw, detection of ARM CPU features on windows follows a pattern of checking specially named entries in the registry over in HKEY_LOCAL_MACHINE\HARDWARE\DESCRIPTION\System\CentralProcessor. For example(From my thinkpad x13s):

CP 4000: MIDR_EL1
CP 4020: ID_AA64PFR0_EL1
CP 4021: ID_AA64PFR1_EL1
CP 4028: ID_AA64DFR0_EL1
CP 4029: ID_AA64DFR1_EL1
CP 402C: ID_AA64AFR0_EL1
CP 402D: ID_AA64AFR1_EL1
CP 4030: ID_AA64ISAR0_EL1
CP 4031: ID_AA64ISAR1_EL1
CP 4038: ID_AA64MMFR0_EL1
CP 4039: ID_AA64MMFR1_EL1
CP 403A: ID_AA64MMFR2_EL1

The CP #### format is based on the encoding of the register's identifier when passed into the MRS instruction: (op0&1):op1:crn:crm:op2. Reading the ID_AA64ISAR2_EL1 register on Windows to detect FEAT_LUT in this case would be in a CP 4032 registry-entry.

Ah, thanks that should future proof things a bit more. Though it looks like our CI is too old for even the Linux builds to finish.

@mediouni-m
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fwiw, detection of ARM CPU features on windows follows a pattern of checking specially named entries in the registry over in HKEY_LOCAL_MACHINE\HARDWARE\DESCRIPTION\System\CentralProcessor. For example(From my thinkpad x13s)

Please don't use those entries if you can, they're an internal implementation detail and aren't sanitised to only the feature set a given Windows release supports.

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